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w29ee012 128k 8 cmos flash memory publication release date: march 26, 2002 - 1 - revision a3 general description the w29ee012 is a 1 - megabit, 5 - volt only cmos flash memory organized as 128k 8 bits. the device can be programmed and erased in - system with a standard 5v power supply. a 12 - volt v pp is not required. the unique cell architecture of the w29ee012 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5 - volt flash memory products). the device can also be programmed and erased using standard eprom programmers. features single 5 - volt program and erase operations fast page - write operations - 128 bytes per page - page program cycle: 10 ms (max.) - effective byte - program cycle time: 39 m s - optional software - protected d ata write fast chip - erase operation: 50 ms page program/erase cycles: 1,000 ten - year data retention software and hardware da ta protection low power consumption - active current: 25 ma (typ.) - standby current: 20 m a (typ.) automatic program timing with internal v pp generation end of program detection - toggle bit - data polling latched address and data ttl compatible i/o jedec standard byte - wide pinouts
w29ee012 - 2 - pin configurations b lock diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a6 a3 a2 a1 a0 nc a16 a15 a12 a7 a5 a4 dq0 dq1 dq2 gnd v #we nc a14 a13 a8 a9 a11 #oe a10 #ce dq7 dq6 dq5 dq4 dq3 dd 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 d q 2 g n d d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 #oe a10 #ce dq7 a 1 2 a 1 6 n c v d d # w e n c a 1 5 32-pin dip 32-pin plcc control output buffer decoder core array #ce #oe #we a0 . . a16 . . dq0 dq7 v dd v ss pin description symbol pin name a0 - a16 address inputs dq0 - dq7 data inputs/outputs #ce chip enable #oe output enable #we write enable v dd power supply gnd gro und nc no connection
w29ee012 publication release date: march 26, 2002 - 3 - revision a3 functional descripti on read mode the read operation of the w29ee012 is controlled by #ce and #oe, both of which have to be low for the host to obtain data from the outputs. #ce is used for device selection. when #ce is high, the c hip is de - selected and only standby power will be consumed. #oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either #ce or #oe is high. refer to the timing waveforms for further details. page write mode the w29ee012 is programmed on a page basis. every page contains 128 bytes of data. if a byte of data within a page is to be changed, data for the entire page must be loaded into the device. any byte that is not loaded will be erased to "ffh " during programming of the page. the write operation is initiated by forcing #ce and #we low and #oe high. the write procedure consists of two steps. step 1 is the byte - load cycle, in which the host writes to the page buffer of the device. step 2 is an i nternal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non - volatile storage. during the byte - load cycle, the addresses are latched by the falling edge of either #ce or #we, whichever occurs last. the data are latched by the rising edge of either #ce or #we, whichever occurs first. if the host loads a second byte into the page buffer within a byte - load cycle time (t blc ) of 200 m s, after the initial byte - load cycle, the w29ee012 will stay in the page load cycle. additional bytes can then be loaded consecutively. the page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer within 300 m s (t blco ) from the last byte - load cycle, i.e., there is no subsequent #we high - to - low transition after the last rising edge of #we. a 7 to a 16 specify the page address. all bytes that are loaded into the page buffer must have the same page address. a 0 to a 6 specify the byte address within the page. the bytes may be loaded in any order; sequential loading is not required. in the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. before the completion of the int ernal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. software - protected data write the device provides a jedec - approved optional software - protected data write. once this scheme is enabled, any write operation requires a series of three - byte program commands (with specific data to a specific address) to be performed before the data load operation. the three - byte load command sequence begins the page load c ycle, without which the write operation will not be activated. this write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power - up and power - down. the w29ee012 is shipped with the softwa re data unprotection enabled. to enable the software data protection scheme, perform the three - byte command cycle at the beginning of a page load cycle. the device will then enter the software data protection mode, and any subsequent write operation must b e preceded by the three - byte program command cycle. once enabled, the software data protection will remain enabled unless the disable commands are issued. a power transition will not reset the software data protection feature. to reset the device to unprot ected mode, a six - byte command sequence is required. see table 3 for specific codes and figure 10 for the timing diagram.
w29ee012 - 4 - hardware data protection the integrity of the data stored in the w29ee012 is also hardware protected in the following ways: (1) nois e/glitch protection: a #we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming and operation are inhibited when v dd is less than 3.8v. (3) write inhibit mode: forcing #oe low, #ce high, or #we high will inhibit the write operation. this prevents inadvertent writes during power - up or power - down periods. data polling (dq 7 ) - write status detection the w29ee012 includes a data polling feature to indicate the end of a programming cycle. when th e w29ee012 is in the internal programming cycle, any attempt to read dq 7 of the last byte loaded during the page/byte - load cycle will receive the complement of the true data. once the programming cycle is completed. dq 7 will show the true data. toggle bit (dq 6 ) - write status detection in addition to data polling, the w29ee012 provides another method for determining the end of a program cycle. during the internal programming cycle, any consecutive attempts to read dq 6 will produce alternating 0's and 1's. whe n the programming cycle is completed, this toggling between 0's and 1's will stop. the device is then ready for the next operation. 5 - volt - only software chip erase the chip - erase mode can be initiated by a six - byte command sequence. after the command loadi ng cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 ms. the host system is not required to provide any control or timing during this operation. product identification the product id operation outputs the manufacturer code and device code. programming equipment automatically matches the device with its proper erase and programming algorithms. the manufacturer and device codes can be accessed by software or hardware operation. in the software acc ess mode, a six - byte command sequence can be used to access the product id. a read from address 0000h outputs the manufacturer code (dah). a read from address 0001h outputs the device code (c1h). the product id operation can be terminated by a three - byte c ommand sequence. in the hardware access mode, access to the product id is activated by forcing #ce and #oe low, #we high, and raising a9 to 12 volts. note: the hardware sid read function is not included in all parts; please refer to ordering information for details.
w29ee012 publication release date: march 26, 2002 - 5 - revision a3 table of operating m odes operating mode selection operating range = 0 to 70 c (ambient temperature), v dd = 5v 10 % , v ss = 0v, v hh = 12v mode pins #ce #oe #we address dq. read v il v il v ih a in dout write v il v ih v il a in din standby v ih x x x high z write inhibit x v il x x high z/d out x x v ih x high z/d out output disable x v ih x x high z 5 - volt software chip erase v il v ih v il a in d in product id v il v il v ih a0 = v il ; a1 - a16 = v il ; a9 = v hh manufacturer code da (hex) v il v il v ih a0 = v i h ; a1 - a16 = v il ; a9 = v hh device code c1 (hex)
w29ee012 - 6 - command codes for software data protection byte sequence to enable protection to disable protectio n address data address data 0 write 5555h aah 5555h aah 1 write 2aaah 55h 2aaah 55h 2 write 5555h a0h 5555h 80h 3 write - - 5555h aah 4 write - - 2aaah 55h 5 write - - 5555h 20h software data protection acquisition flow software data protection enable flow load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 software data protection disable flow notes for software program code: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex)
w29ee012 publication release date: march 26, 2002 - 7 - revision a3 command codes for software chip erase byte sequence address data 0 write 5555h aah 1 write 2aaah 55h 2 write 5555h 80h 3 write 5555h aah 4 write 2aaah 55h 5 write 5555h 10h sofware chip erase acquisition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 10 to address 5555 notes for software chip erase: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex)
w29ee012 - 8 - command codes for product identification byte sequence software product identification entry software product identification exit address data address data 0 write 5555h aah 5555h aah 1 write 2aaah 55h 2aaah 55h 2 write 5555h 80h 5555h f0h 3 write 5555h aah - - 4 write 2aaah 55h - - 5 write 5555h 60h - - pause 10 m s pause 10 m s software product identification acquisition flow product identification entry(1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 60 to address 5555 pause 10 s product identification mode(2,3) read address = 0 data = da read address = 1 data = c1 product identification exit(1) load data aa to address 5555 load data 55 to address 2aaa load data fo to address 5555 pause 10 m m s normal mode (4) m notes for software product identification: (1) data format: dq7 - dq0 (hex); address format: a14 - a0 (hex). (2) a1 - a16 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification mode if power d own. (4) the device returns to standard operation mode.
w29ee012 publication release date: march 26, 2002 - 9 - revision a3 dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential - 0.5 to +7.0 v operating temperature 0 to +70 c storage temperature - 65 to +150 c d.c. voltage on any pin to ground potential except #oe - 0.5 to v dd +1.0 v transient voltage ( 20 ns) on any pin to ground potential - 1.0 to v dd +1.0 v voltage on #oe pin to ground potential - 0.5 to 12.5 v note: exposure to conditions beyond those listed unde r absolute maximum ratings may adversely affect the life and reliability of the device. operating characteristics (v dd = 5.0v 10 % , v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions limits unit min. typ. max. power supply current i cc #ce = #oe = v il , #we = v ih , all i/os open address inputs = v il /v ih , at f = 5 mhz - - 50 ma standby v dd current (ttl input) i sb 1 #ce = v ih , all i/os open other inputs = v il /v ih - 2 3 ma standby v dd current (cmos input) i sb 2 #ce = v dd - 0.3v, all i/os open oth er inputs = v dd - 0.3v/gnd - 20 100 m a input leakage current i li v in = gnd to v dd - - 1 m a output leakage current i lo v in = gnd to v dd - - 10 m a input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = - 0.4 ma 2.4 - - v power - up timing parameter symbol typical unit power - up to read operation t pu .read 100 m s power - up to write operation t pu .write 5 ms
w29ee012 - 10 - capacitance (v dd = 5.0v, t a = 25 c, f = 1 mh z) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf ac characteristics ac test conditions (v dd = 5v 10 % ) parameter conditions 90 ns/120 ns 150 ns input pulse levels 0v/3v 0v/3v input rise/fall time 5 ns 10 ns input/output timing level 1.5v/1.5v 1.5v/1.5v output load 1 ttl gate and c l = 100 pf 1 ttl gate and c l = 100 pf ac test load and waveforms 3.0v 0v 1.5v test point test point 1.5v input output +5v 1.8k ohm d out 1.3k ohm 100 pf for 90/120/150 ns (including jig and scope)
w29ee012 publication release date: march 26, 2002 - 11 - revision a3 read cycle timing parameters (v dd = 5.0v 10 % , v ss = 0v, t a = 0 to 70 c) parameter sym. w29ee012 unit min. max. read cycle time t rc 150 - ns chip enable access time t ce - 150 ns address access time t aa - 150 ns output enable access time t oe - 70 ns #ce low to active output t clz 0 - ns #oe low to active output t olz 0 - ns #ce high to high - z output t chz - 45 ns #oe high to high - z output t ohz - 45 ns output hold from address change t oh 0 - ns byte/page - write cycle timing parameters parameter symbol min. typ. max. unit write cycle (erase and pro gram) t wc - - 10 ms address setup time t as 0 - - ns address hold time t ah 50 - - ns #we and #ce setup time t cs 0 - - ns #we and #ce hold time t ch 0 - - ns #oe high setup time t oes 10 - - ns #oe high hold time t oeh 10 - - ns #ce pulse width t cp 70 - - ns #we pulse width t wp 70 - - ns #we high width t wph 150 - - ns data setup time t ds 50 - - ns data hold time t dh 10 - - ns byte load cycle time t blc 0.22 - 200 m s byte load cycle time - out t blco 300 - - m s note: all ac timing signals observe the fo llowing guidelines for determining setup and hold times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
w29ee012 - 12 - data polling and toggle bit timing parameters parameter sym. w29ee012 - 90 w29ee012 - 12 w29ee012 - 1 5 unit min. max. min. max. min. max. #oe to data polling output delay t oep - 45 - 60 - 70 ns #ce to data polling output delay t cep - 90 - 120 - 150 ns #oe to toggle bit output delay t oet - 45 - 60 - 70 ns #ce to toggle bit output delay t cet - 90 - 120 - 150 ns timing waveforms read cycle timing diagram address a16-0 dq7-0 data valid data valid high-z #ce #oe #we t rc v ih t olz t clz t oe t ce t oh t aa t chz t ohz high-z
w29ee012 publication release date: march 26, 2002 - 13 - revision a3 timing waveforms, continued #we controlled write cycle timing diagram address a16-0 dq7-0 data valid internal write starts #ce #oe #we t as t cs t oes t ah t blco t wc t ch t oeh t wph t wp t ds t dh #ce controlled write cycle timing diagram high z data valid internal write starts #ce #oe #we dq7-0 t as t ah t blco t wc t cph t oeh t dh t ds t cp t oes address a16-0
w29ee012 - 14 - timing waveforms, continued page write cycle timing diagram address a16-0 byte 0 byte 1 byte 2 byte n-1 byte n internal write start dq7-0 #ce #oe #we t wc t blco t blc t wph t wp #data polling timing diagram address a16-0 dq7-0 #we #oe #ce t x x x x t cep t oeh t oep t oes wc
w29ee012 publication release date: march 26, 2002 - 15 - revision a3 timing waveforms, continued toggle bit timing diagram address a16-0 dq6 #ce #oe #we t oeh t oes t wc page write timing diagram software data protection mode 5555 5555 aa 55 a0 three-byte sequence for software data protection mode byte/page load cycle starts internal write starts byte n (last byte) byte 0 sw2 sw1 sw0 address a16-0 dq6 #ce #oe #we 2aaa t wp t wph t blc t blco byte n-1 t wc
w29ee012 - 16 - timing waveforms, continued reset software data protection timing diagram sw2 sw1 sw0 address a16-0 dq7-0 #ce #oe #we sw3 sw4 sw5 internal programming starts six-byte sequence for resetting software data protection mode t wc t wp t wph t blc t blco 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 20 5 volt - only software chip erase timing diagram sw2 sw1 sw0 address a16-0 dq7-0 #ce #oe #we sw3 sw4 sw5 internal programming starts six-byte code for 5v-only software chip erase t wc t wp t wph t blc t blco 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10
w29ee012 publication release date: march 26, 2002 - 17 - revision a3 ordering information part no. access time ( n s) power supply current max. ( m a) standby v dd current max. ( m a) package hardware sid read function w29ee012 50 100 - y notes: 1. winbond reserves the right to make changes t o its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. in hardware sid read column: y = with sid read function; n = without sid read function.
w29ee012 - 18 - bonding pad diagram x y 4 a12 a7 4 5 a14 30 31 #we a13 29 3 a15 a16 2 1 28 a8 27 a9 10 a2 #ce 23 #oe 25 24 a10 ra8014 15 dq2 16 gnd 13 dq0 dq1 14 12 a0 9 a3 a5 6 7 a4 a6 6 gnd 17s -1 17s -2 gnd 21 dq6 22 dq7 20 dq5 18 dq3 dq4 19 11 a1 26 a11 32 33s -2 vcc vcc 33s -1 vcc pad no. x y 1 - 187.04 1920.30 2 - 380.84 1920.30 3 - 517.64 1920.30 4 - 1121.73 1920.30 5 - 1258.52 1920.30 6 - 148 4.75 1901.22 7 - 1484.75 1713.42 8 - 1484.75 1576.62 9 - 1453.92 - 1577.46 10 - 1453.92 - 1742.70 11 - 1453.92 - 1879.50 12 - 1240.62 - 1923.06 13 - 977.19 - 1921.98 14 - 727.22 - 1921.98 15 - 504.26 - 1921.98 16 - 264.72 - 1900.20 17s - 1 - 86.90 - 1900.20 17 s - 2 - 1 .70 - 1900.20 18 286.06 - 1909.98 19 509.01 - 1909.98 20 758.98 - 1909.98 21 981.94 - 1909.98 22 1231.90 - 1909.98 23 1469.29 - 1897.26 24 1468.29 - 1708.32 25 1469.29 - 1571.52 26 1476.60 1564.62 27 1476.60 1752.42 28 1476.60 1889.22 29 1311.85 1920.30 30 891.00 1920.30 31 523.36 1920.30 32 310.36 1914.24 33s - 1 180.16 1914.24 33 s - 2 94.96 1914.24 n ote: for bare chip form (c.o.b.) applications, the substrate must be connected to v dd or left floating in the pcb layout.
w29ee012 publication release date: march 26, 2002 - 19 - revision a3 version history version date page description a1 jan. 1997 - initial issued a2 apr. 2000 10 modify v ih /v il = 0v/3v and v oh /v ol = 1.5v/1.5v a3 mar. 26, 2002 1, 17, 19, 20 delete package description 1,11 delete access time 4, 17 add in hardware sid read function note 4 modif y v dd power up/down detection in hardware data protection 18 add bonding pad diagram headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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